An MOS transistor having a trench gate structure offers important advantages over a planar transistor for high current, low voltage switching applications. The DMOS trench gate typically includes a trench extending from the source to the drain and having sidewalls and a floor that are each lined with a layer of thermally grown silicon dioxide. The lined trench is filled with doped polysilicon. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in an MOS channel extending along the vertical sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the contribution of the channel to on-resistance. The structure and performance of trench DMOS transistors are discussed in Bulucea and Rossen, "Trench DMOS Transistor Technology for High-Current (100 A Range) Switching," in Solid-State Electronics, 1991, Vol. 34, No. 5, pp 493-507, the disclosure of which is incorporated herein by reference. In addition to their utility in DMOS devices, trench gates are also advantageously employed in insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), and other MOS-gated devices.
FIG. 1 schematically depicts the cross-section of a trench-gated N-type MOSFET device 100 of the prior art formed on an upper layer 101a of an N+ substrate 101. Device 100 includes a trench 102 whose sidewalls 104 and floor 103 are lined with a gate dielectric such as silicon dioxide. Trench 102 is filled with a conductive material 105 such as doped polysilicon, which serves as an electrode for gate region 106.
Upper layer 101a of substrate 101 further includes P-well regions 107 overlying an N-drain zone 108. Disposed within P-well regions 107 at an upper surface 109 of upper layer 101a are heavily doped P+ body regions 110 and heavily doped N+ source regions 111. An interlevel dielectric layer 112 is formed over gate region 106 and source regions 111. Contact openings 113 enable metal layer 114 to contact body regions 110 and source regions 111. The rear side 115 of N+ substrate 101 serves as a drain.
Although FIG. 1 shows only one MOSFET, a typical device currently employed in the industry consists of an array of them arranged in various cellular or stripe layouts. As a result of recent semiconductor manufacturing improvements enabling increased densities of trench gated devices, the major loss in a device when in a conduction mode occurs in its lower zone, i.e., increased drain resistivity. Because the level of drain doping is typically determined by the required voltage blocking capability, increased drain doping for reducing resistivity is not an option. Thus, there is a need for reducing the resistivity of the drain region in a semiconductor device without also reducing its blocking capability. The present invention meets this need.